An apparatus includes multiple first memory circuits, in which the multiple first memory circuits are positioned on at least one dual in-line memory module (DIMM). The apparatus includes an interface circuit operable to interface the first memory circuits with a system; present the first memory circuits to the system as one or more simulated second memory circuits; transmit, in response to receiving a first refresh control signal sent from the system to the one or more simulated memory circuits, multiple second refresh control signals to the first memory circuits; and apply a respective delay to each second refresh control signal transmitted to a corresponding first memory circuit. Each simulated second memory circuit has a corresponding second memory capacity that is greater than a first memory capacity of at least one of the first memory circuits.