Invention Grant
US08775493B2 Double-step CORDIC processing for conventional signed arithmetic with decision postponing
有权
具有决策延期功能的常规带符号算法的双步CORDIC处理
- Patent Title: Double-step CORDIC processing for conventional signed arithmetic with decision postponing
- Patent Title (中): 具有决策延期功能的常规带符号算法的双步CORDIC处理
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Application No.: US13085616Application Date: 2011-04-13
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Publication No.: US08775493B2Publication Date: 2014-07-08
- Inventor: Siva Swaroop Vontela , Vidya Prabhu , Priyabrata Kundu
- Applicant: Siva Swaroop Vontela , Vidya Prabhu , Priyabrata Kundu
- Applicant Address: US CA San Jose
- Assignee: LSI Corporation
- Current Assignee: LSI Corporation
- Current Assignee Address: US CA San Jose
- Agency: Mendelsohn, Drucker & Dunleavy, P.C.
- Agent Steve Mendelsohn
- Main IPC: G06F7/38
- IPC: G06F7/38
Abstract:
A double-step CORDIC algorithm is implemented for conventional signed arithmetic using multiple iteration stages in which at least one stage implements decision postponing, in which the decision for each stage is delayed until the next stage. In one implementation, the decision for the previous stage is implemented in parallel with the execution of CORDIC equation functions for the current stage. Implementing the double-step CORDIC with decision postponing algorithm can increase the speed of the CORDIC function compared to prior-art CORDIC implementations.
Public/Granted literature
- US20120265796A1 Double-Step CORDIC Processing for Conventional Signed Arithmetic With Decision Postponing Public/Granted day:2012-10-18
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