Invention Grant
US08775750B2 Interleaver with parallel address queue arbitration dependent on which queues are empty
有权
具有并行地址队列仲裁的交织器取决于哪些队列为空
- Patent Title: Interleaver with parallel address queue arbitration dependent on which queues are empty
- Patent Title (中): 具有并行地址队列仲裁的交织器取决于哪些队列为空
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Application No.: US13496472Application Date: 2009-09-16
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Publication No.: US08775750B2Publication Date: 2014-07-08
- Inventor: Sheng Wei Chong , Hiroyuki Igura
- Applicant: Sheng Wei Chong , Hiroyuki Igura
- Applicant Address: JP Tokyo
- Assignee: Nec Corporation
- Current Assignee: Nec Corporation
- Current Assignee Address: JP Tokyo
- Agency: McGinn IP Law Group, PLLC
- International Application: PCT/JP2009/066717 WO 20090916
- International Announcement: WO2011/033680 WO 20110324
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/06 ; H03M13/27

Abstract:
An interleaving method includes: generating multiple read-addresses for respective bits of multiple write-words; queuing the read-addresses in parallel in multiple address queues; selecting an address queue among the address queues that is not empty based on status of each address queue; decoding the address from the selected address queue to a read-address and a bit-address; extracting a read-word from data to be interleaved based on the read-address; selecting a write-bit from the read-word based on the bit-address; arbitrating an individual write-bit to one of the write-words based on an address queue ID of the selected address queue; and generating write-addresses for respective write-words.
Public/Granted literature
- US20120173829A1 INTERLEAVER AND INTERLEAVING METHOD Public/Granted day:2012-07-05
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