A memory controller is for controlling access to a memory device of the type having a non-uniform access timing characteristic. An interface receives transactions issued from at least one transaction source and a buffer temporarily stores as pending transactions those transactions received by the interface that have not yet been issued to the memory device. The buffer maintains a plurality of ordered lists (having a number of entries) for the stored pending transactions, including at least one priority based ordered list and at least one access timing ordered list. Each entry being associated with one of the pending transactions, and ordered within its priority based ordered list based on the priority indication of the associated pending transaction. Arbitration circuitry performs an arbitration operation during which the plurality of ordered lists are referenced so as to select a winning transaction to be issued to the memory device.