Invention Grant
- Patent Title: Reducing memory used to store totals in static timing analysis
- Patent Title (中): 减少用于在静态时序分析中存储总计的内存
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Application No.: US13095719Application Date: 2011-04-27
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Publication No.: US08775855B2Publication Date: 2014-07-08
- Inventor: Sarvesh Bhardwaj , Khalid Rahmat , Kayhan Kucukcakar , Rachid Helaihel
- Applicant: Sarvesh Bhardwaj , Khalid Rahmat , Kayhan Kucukcakar , Rachid Helaihel
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Fenwick & West LLP
- Main IPC: G06F1/00
- IPC: G06F1/00

Abstract:
A system and a method are disclosed for reducing memory used in storing totals during static timing analysis. Totals are stored at various points along paths analyzed in static timing analysis. Some totals may not be merged for reasons including differing clock re-convergence pessimism removal (CRPR) dominators, exceptions, or clocks. Totals at a point may be stored in a super-tag mapping table and replaced at the point with a super-tag. The super-tag includes a super-tag ID referencing the totals stored in the super-tag mapping table. The super-tag also includes a time delay value. The time delay value allows the super-tag ID to be reused in other super-tags at other points while still storing total time delays at the other points. Therefore, the memory used to store totals is reduced in many situations.
Public/Granted literature
- US20120278647A1 Reducing Memory Used To Store Totals In Static Timing Analysis Public/Granted day:2012-11-01
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