Invention Grant
US08775857B2 Sequential on-chip clock controller with dynamic bypass for multi-clock domain testing
有权
具有动态旁路功能的片上时钟控制器，用于多时钟域测试
- Patent Title: Sequential on-chip clock controller with dynamic bypass for multi-clock domain testing
- Patent Title (中): 具有动态旁路功能的片上时钟控制器，用于多时钟域测试
-
Application No.: US13152013Application Date: 2011-06-02
-
Publication No.: US08775857B2Publication Date: 2014-07-08
- Inventor: Shray Khullar , Swapnil Bahl
- Applicant: Shray Khullar , Swapnil Bahl
- Applicant Address: NL Amsterdam
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: NL Amsterdam
- Agency: Gardere Wynne Sewell LLP
- Priority: IN3130/DEL/2010 20101228
- Main IPC: G06F1/08
- IPC: G06F1/08 ; G06F1/06 ; G06F11/22 ; G01R31/3185
Abstract:
A controller includes a clock control unit configured to provide a first output to test circuitry and a bypass unit configured to provide a second output to a further controller. The controller is configured to cause the bypass unit to output the second output and to optionally cause the clock control unit to output the first output.
Public/Granted literature
- US20120166860A1 SEQUENTIAL ON-CHIP CLOCK CONTROLLER WITH DYNAMIC BYPASS FOR MULTI-CLOCK DOMAIN TESTING Public/Granted day:2012-06-28
Information query
