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US08775896B2 Non-binary LDPC decoder with low latency scheduling 有权
具有低延迟调度的非二进制LDPC解码器

Non-binary LDPC decoder with low latency scheduling
Abstract:
Various embodiments of the present invention provide systems and methods for decoding of non-binary LDPC codes. For example, a low density parity check data decoder is disclosed that includes a variable node processor operable to perform variable node updates based at least in part on check node to variable node message vectors, a check node processor operable to perform check node updates and to generate the check node to variable node message vectors, and a scheduler operable to cause the variable node processor to use check node to variable node message vectors from multiple decoding iterations when performing the variable node updates for a given decoding iteration.
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