Invention Grant
- Patent Title: Non-binary LDPC decoder with low latency scheduling
- Patent Title (中): 具有低延迟调度的非二进制LDPC解码器
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Application No.: US13369468Application Date: 2012-02-09
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Publication No.: US08775896B2Publication Date: 2014-07-08
- Inventor: Zongwang Li , Chung-Li Wang , Changyou Xu
- Applicant: Zongwang Li , Chung-Li Wang , Changyou Xu
- Applicant Address: US CA Milpitas
- Assignee: LSI Corporation
- Current Assignee: LSI Corporation
- Current Assignee Address: US CA Milpitas
- Agency: Hamilton DeSanctis & Cha
- Main IPC: H03M13/00
- IPC: H03M13/00

Abstract:
Various embodiments of the present invention provide systems and methods for decoding of non-binary LDPC codes. For example, a low density parity check data decoder is disclosed that includes a variable node processor operable to perform variable node updates based at least in part on check node to variable node message vectors, a check node processor operable to perform check node updates and to generate the check node to variable node message vectors, and a scheduler operable to cause the variable node processor to use check node to variable node message vectors from multiple decoding iterations when performing the variable node updates for a given decoding iteration.
Public/Granted literature
- US20130212447A1 Non-Binary LDPC Decoder with Low Latency Scheduling Public/Granted day:2013-08-15
Information query
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