Invention Grant
- Patent Title: Alignment of microarchitectural conditions
- Patent Title (中): 微结构条件的对齐
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Application No.: US13929102Application Date: 2013-06-27
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Publication No.: US08775990B1Publication Date: 2014-07-08
- Inventor: Peter J. Smith , Bharat S. Pillilli , Harikrishna B. Baliga , Michael S. Yu , Shlomi Alkalay
- Applicant: Peter J. Smith , Bharat S. Pillilli , Harikrishna B. Baliga , Michael S. Yu , Shlomi Alkalay
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Patent Capital Group
- Main IPC: G06F9/455
- IPC: G06F9/455 ; G06F17/50

Abstract:
Techniques for controlling alignment of conditions between modular functional blocks in an integrated circuit having a hierarchical network of modular functional blocks. The output of each functional block can be logically determined by its external inputs combined with internal state feedback and internal state and is derived from a pattern of prior external inputs. Alignment of output conditions from independent and interdependent functional blocks within the hierarchical network of functional blocks is induced to provide unique conditions by modifying internal state and timing alignments with internal data and internal controls within one or more of the modular functional blocks. Functional outputs from one or more of the modular functional blocks can be monitored based on the modified internal state and timing alignments. Pattern results can be generated based on the monitoring. Test results based on the pattern results can be stored.
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