Invention Grant
- Patent Title: Integrated circuit design flow with layout-dependent effects
- Patent Title (中): 集成电路设计流程与布局相关的效果
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Application No.: US13601773Application Date: 2012-08-31
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Publication No.: US08775993B2Publication Date: 2014-07-08
- Inventor: Mu-Jen Huang , Yu-Sian Jiang , Chien-Wen Chen
- Applicant: Mu-Jen Huang , Yu-Sian Jiang , Chien-Wen Chen
- Applicant Address: TW
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW
- Agency: Lowe Hauptman & Ham, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A design system for designing an integrated circuit that includes a processor, a memory coupled to the processor, and instructions to generate and edit a schematic of the integrated circuit, generate at least one recommended layout parameter of an integrated circuit device within the integrated circuit, extract the at least one recommended layout parameter during a layout stage of the integrated circuit, and calculate a circuit performance parameter of the integrated circuit using the at least one recommended layout parameter, and a user interface configured to display at least one of the circuit performance parameter and layout constraints of the integrated circuit device of the integrated circuit.
Public/Granted literature
- US20140068540A1 INTEGRATED CIRCUIT DESIGN FLOW WITH LAYOUT-DEPENDENT EFFECTS Public/Granted day:2014-03-06
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