Invention Grant
- Patent Title: Using entire area of chip in TDDB checking
- Patent Title (中): 在TDDB检查中使用芯片的整个区域
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Application No.: US13837561Application Date: 2013-03-15
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Publication No.: US08775994B2Publication Date: 2014-07-08
- Inventor: Bonnie E. Weir , Kausar Banoo
- Applicant: LSI Corporation
- Applicant Address: US CA San Jose
- Assignee: LSI Corporation
- Current Assignee: LSI Corporation
- Current Assignee Address: US CA San Jose
- Agency: Cochran Freund & Young LLC
- Agent Alexander J. Neudeck
- Main IPC: G06F9/455
- IPC: G06F9/455 ; G06F17/50
Abstract:
A method for checking for reliability problems of an integrated circuit that includes determining a total MOS transistor gate area for an entire integrated circuit. Based on the total MOS transistor gate area, a time dependent dielectric breakdown lifetime (TDDB) is calculated.
Public/Granted literature
- US20140096098A1 USING ENTIRE AREA OF CHIP IN TDDB CHECKING Public/Granted day:2014-04-03
Information query
