A hybrid bit detection circuit for receiving bits from different global positioning systems, e.g. GPS and GLONASS, can include a frequency lock loop (FLL) for receiving the global positioning bits and removing Doppler frequency error and an integrate and dump (I&D) block coupled to an output of the FLL. A coherent detection circuit can be coupled to an output of the FLL and an output of the integrated and dump block. A differential detection circuit can be coupled to an output of the I&D block. Two parity check blocks can be coupled to outputs of the coherent and differential detection circuits.