Invention Grant
- Patent Title: Memory device and system including a memory device electronically connectable to a host circuit
- Patent Title (中): 存储器件和系统,包括可与电路连接的存储器件
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Application No.: US12751438Application Date: 2010-03-31
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Publication No.: US08782326B2Publication Date: 2014-07-15
- Inventor: Yasuhiko Kosugi
- Applicant: Yasuhiko Kosugi
- Applicant Address: JP Tokyo
- Assignee: Seiko Epson Corporation
- Current Assignee: Seiko Epson Corporation
- Current Assignee Address: JP Tokyo
- Agency: Stroock & Stroock & Lavan LLP
- Priority: JP2009-088593 20090401; JP2009-195318 20090826
- Main IPC: G06F11/07
- IPC: G06F11/07 ; G06F12/16

Abstract:
A memory includes a nonvolatile memory cell array, and a memory control circuit which carries out writing of data to and reading of data from the memory cell array in access units of N bits where N is an integer equal to 2 or greater. The memory cell array includes a rewritable area in which both writing of data and reading of data are permissible, and a read-only area in which writing of data is prohibited and reading of data is permissible. The rewritable area is configured so that the N bits constituting one access unit contain both actual data and an error detection code. The read-only area is divided between an actual data area in which the N bits constituting one access unit contain actual data, and an error detection code area in which the N bits constituting one access unit contain error detection codes.
Public/Granted literature
- US20100257327A1 MEMORY DEVICE AND SYSTEM INCLUDING A MEMORY DEVICE ELECTRONICALLY CONNECTABLE TO A HOST CIRCUIT Public/Granted day:2010-10-07
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