Invention Grant
- Patent Title: Hierarchical channel marking in a memory system
- Patent Title (中): 内存系统中的分层通道标记
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Application No.: US13353925Application Date: 2012-01-19
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Publication No.: US08782485B2Publication Date: 2014-07-15
- Inventor: Patrick J. Meaney , Eldee Stephens , Luis A. Lastras-Montano , Judy S. Johnson
- Applicant: Patrick J. Meaney , Eldee Stephens , Luis A. Lastras-Montano , Judy S. Johnson
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Margaret McNamara
- Main IPC: H03M13/00
- IPC: H03M13/00

Abstract:
Channel marking is provided in a memory system that includes a first memory channel, a second memory channel, and error correction code (ECC) logic. The memory system is configured to perform a method that includes receiving a request to apply a first channel mark to the first memory channel and determining a priority level of the first channel mark. A request is received to apply a second channel mark to the second memory channel, and a priority level of the second mark is determined. It is determined that the priority level of the first channel mark is higher than the priority level of the second channel mark. The first channel mark is supplied to the ECC logic while blocking the second channel mark from the ECC logic.
Public/Granted literature
- US20130191698A1 HIERARCHICAL CHANNEL MARKING IN A MEMORY SYSTEM Public/Granted day:2013-07-25
Information query
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