Silicon germanium mask for deep silicon etching

Invention Grant

US08791021B2 Silicon germanium mask for deep silicon etching 有权

Title translation: 用于深硅蚀刻的硅锗掩模

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Patent Title: Silicon germanium mask for deep silicon etching
Patent Title (中): 用于深硅蚀刻的硅锗掩模
Application No.: US13409868

Application Date: 2012-03-01
Publication No.: US08791021B2

Publication Date: 2014-07-29
Inventor: Mohamed Serry , Andrew Rubin , Mohamed Refaat , Sherif Sedky , Mohammad Abdo
Applicant: Mohamed Serry , Andrew Rubin , Mohamed Refaat , Sherif Sedky , Mohammad Abdo
Applicant Address: SA Thuwal
Assignee: King Abdullah University of Science and Technology
Current Assignee: King Abdullah University of Science and Technology
Current Assignee Address: SA Thuwal
Agency: Steptoe & Johnson LLP
Main IPC: H01L21/311
IPC: H01L21/311

Silicon germanium mask for deep silicon etching

Abstract:

Polycrystalline silicon germanium (SiGe) can offer excellent etch selectivity to silicon during cryogenic deep reactive ion etching in an SF6/O2 plasma. Etch selectivity of over 800:1 (Si:SiGe) may be achieved at etch temperatures from −80 degrees Celsius to −140 degrees Celsius. High aspect ratio structures with high resolution may be patterned into Si substrates using SiGe as a hard mask layer for construction of microelectromechanical systems (MEMS) devices and semiconductor devices.

Abstract(Chinese):

在SF6 / O2等离子体的低温深反应离子蚀刻中，多晶硅锗（SiGe）可以提供优异的硅蚀刻选择性。在-80摄氏度至-140摄氏度的蚀刻温度下，可获得超过800：1（Si：SiGe）的蚀刻选择性。可以使用SiGe作为用于构建微机电系统（MEMS）器件和半导体器件的硬掩模层来将具有高分辨率的高纵横比结构图案化为Si衬底。

Public/Granted literature

US20120225557A1 SILICON GERMANIUM MASK FOR DEEP SILICON ETCHING Public/Granted day:2012-09-06

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02	.半导体器件或其部件的制造或处理
H01L21/04	..至少具有一个跃变势垒或表面势垒的器件，例如PN结、耗尽层、载体集结层
H01L21/18	...器件有由周期表Ⅳ族元素或含有/不含有杂质的AⅢBⅤ族化合物构成的半导体，如掺杂材料
H01L21/30	....用H01L21/20至H01L21/26各组不包含的方法或设备处理半导体材料的（在半导体材料上制作电极的入H01L21/28）
H01L21/31	.....在半导体材料上形成绝缘层的，例如用于掩膜的或应用光刻技术的（密封层入H01L21/56）；以及这些层的后处理；这些层的材料的选择
H01L21/3105	......后处理
H01L21/311	.......绝缘层的刻蚀