Invention Grant
- Patent Title: Substrate breakdown voltage improvement for group III-nitride on a silicon substrate
- Patent Title (中): 硅衬底上III族氮化物的衬底击穿电压提高
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Application No.: US13277692Application Date: 2011-10-20
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Publication No.: US08791504B2Publication Date: 2014-07-29
- Inventor: Chi-Ming Chen , Po-Chun Liu , Hung-Ta Lin , Chin-Cheng Chang , Chung-Yi Yu , Chia-Shiung Tsai , Ho-Yung David Hwang
- Applicant: Chi-Ming Chen , Po-Chun Liu , Hung-Ta Lin , Chin-Cheng Chang , Chung-Yi Yu , Chia-Shiung Tsai , Ho-Yung David Hwang
- Applicant Address: TW
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW
- Agency: Lowe Hauptman & Ham, LLP
- Main IPC: H01L29/66
- IPC: H01L29/66

Abstract:
A circuit structure includes a substrate, a nucleation layer of undoped aluminum nitride, a graded buffer layer comprising aluminum, gallium, nitrogen, one of silicon and oxygen, and a p-type conductivity dopant, a ungraded buffer layer comprising gallium, nitrogen, one of silicon and oxygen, and a p-type conductivity dopant without aluminum, and a bulk layer of undoped gallium nitride over the ungraded buffer layer. The various dopants in the graded buffer layer and the ungraded buffer layer increases resistivity and results in layers having an intrinsically balanced conductivity.
Public/Granted literature
- US20130099243A1 SUBSTRATE BREAKDOWN VOLTAGE IMPROVEMENT FOR GROUP III-NITRIDE ON A SILICON SUBSTRATE Public/Granted day:2013-04-25
Information query
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