Invention Grant
- Patent Title: Semiconductor device having a multilayer interconnection structure
- Patent Title (中): 具有多层互连结构的半导体器件
-
Application No.: US13483044Application Date: 2012-05-29
-
Publication No.: US08791570B2Publication Date: 2014-07-29
- Inventor: Kenichi Watanabe , Tomoji Nakamura , Satoshi Otsuka
- Applicant: Kenichi Watanabe , Tomoji Nakamura , Satoshi Otsuka
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Semiconductor Limited
- Current Assignee: Fujitsu Semiconductor Limited
- Current Assignee Address: JP Yokohama
- Agency: Fujitsu Patent Center
- Priority: JP2006-341823 20061219
- Main IPC: H01L29/04
- IPC: H01L29/04

Abstract:
A semiconductor device includes first and second conductor patterns embedded in a first interlayer insulation film and a third conductor pattern embedded in a second interlayer insulation film, the third conductor pattern including a main part and an extension part, the extension part being electrically connected to the first conductor pattern by a first via-plug, the extension part having a branched pattern closer to the main part compared with the first conductor pattern, the branched pattern making a contact with the second conductor pattern via a second via-plug, each of the main part, extension part including the branched pattern, first via-plug and second via-plug forming a damascene structure.
Public/Granted literature
- US20120261833A1 SEMICONDUCTOR DEVICE HAVING A MULTILAYER INTERCONNECTION STRUCTURE Public/Granted day:2012-10-18
Information query
IPC分类: