Invention Grant
US08791844B2 Modified dynamic element matching for reduced latency in a pipeline analog to digital converter
有权
改进的动态元素匹配,以减少流水线模数转换器的延迟
- Patent Title: Modified dynamic element matching for reduced latency in a pipeline analog to digital converter
- Patent Title (中): 改进的动态元素匹配,以减少流水线模数转换器的延迟
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Application No.: US13489865Application Date: 2012-06-06
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Publication No.: US08791844B2Publication Date: 2014-07-29
- Inventor: Daniel Meacham , Andrea Panigada , Jorge Grilo
- Applicant: Daniel Meacham , Andrea Panigada , Jorge Grilo
- Applicant Address: US AZ Chandler
- Assignee: Microchip Technology Incorporated
- Current Assignee: Microchip Technology Incorporated
- Current Assignee Address: US AZ Chandler
- Agency: King & Spalding L.L.P.
- Main IPC: H03M1/06
- IPC: H03M1/06

Abstract:
A circuit in an analog-to-digital converter (ADC) includes an amplifier configured to receive an output of a backend DAC; a harmonic distortion correction circuit (HDC) coupled to the amplifier and configured to correct distortion components due to the residue amplifier present in a digital signal from the backend ADC, the HDC circuit providing an output to an adder, the adder receiving a coarse digital output from a coarse ADC; and a DAC noise cancellation circuit (DNC) configured to provide an output to the adder, wherein the DNC circuit is configured to correct distortion components due to the DAC present in the digital signal from the backend ADC; wherein the output of the adder is an ADC digital output and wherein the ADC digital output forms an input to the HDC and the DNC.
Public/Granted literature
- US20130027231A1 Modified Dynamic Element Matching For Reduced Latency In A Pipeline Analog To Digital Converter Public/Granted day:2013-01-31
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