Invention Grant
- Patent Title: 3D built-in self-test scheme for 3D assembly defect detection
- Patent Title (中): 3D内置的3D装配缺陷检测自检方案
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Application No.: US13733071Application Date: 2013-01-02
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Publication No.: US08793547B2Publication Date: 2014-07-29
- Inventor: Siang Poh Loh , Chooi Pei Lim
- Applicant: Altera Corporation
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Weaver Austin Villeneuve & Sampson LLP
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G01R31/3177 ; H01L25/065 ; G01R31/3185 ; G01R31/3187

Abstract:
Techniques and mechanisms are provided for an improved built in self-test (BIST) mechanism for 3D assembly defect detection. According to an embodiment of the present disclosure, the described mechanisms and techniques can function to detect defects in interconnects which vertically connect different layers of a 3D device, as well as to detect defects on a 2D layer of a 3D integrated circuit. Additionally, according to an embodiment of the present disclosure, techniques and mechanisms are provided for determining not only the presence of a defect in a given set of interfaces of an integrated circuit, but the particular interface at which a defect may exist.
Public/Granted literature
- US20140189456A1 3D BUILT-IN SELF-TEST SCHEME FOR 3D ASSEMBLY DEFECT DETECTION Public/Granted day:2014-07-03
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