Modifying a hierarchical circuit design includes: accessing hierarchical circuit data in the hierarchical circuit design; performing timing analysis on a selected portion of the hierarchical circuit data to determine whether inter-block timing closure is achieved; and in the event that inter-block timing closure is not achieved, performing a set of one or more fixes on the selected portion of the hierarchical circuit data to achieve inter-block timing closure. The selected portion of the hierarchical circuit data includes a selected portion of top-level block data and a selected portion of lower-level block data. Accessing hierarchical circuit data, performing timing analysis, and in the event that inter-block timing closure is not achieved, performing the set of one or more fixes are performed within a top-level design process.