Methods of forming integrated circuit devices using modified rectangular mask patterns to increase reliability of contacts to electrically conductive lines

Invention Grant

US08796134B2 Methods of forming integrated circuit devices using modified rectangular mask patterns to increase reliability of contacts to electrically conductive lines 有权

Title translation: 使用改进的矩形掩模图案形成集成电路器件以提高与导电线的接触的可靠性的方法

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Patent Title: Methods of forming integrated circuit devices using modified rectangular mask patterns to increase reliability of contacts to electrically conductive lines
Patent Title (中): 使用改进的矩形掩模图案形成集成电路器件以提高与导电线的接触的可靠性的方法
Application No.: US13397038

Application Date: 2012-02-15
Publication No.: US08796134B2

Publication Date: 2014-08-05
Inventor: Chang-Hwa Kim , Ryan L. Burns
Applicant: Chang-Hwa Kim , Ryan L. Burns
Applicant Address: KR US NY Armonk
Assignee: Samsung Electronics Co., Ltd.,International Business Machines Corporation
Current Assignee: Samsung Electronics Co., Ltd.,International Business Machines Corporation
Current Assignee Address: KR US NY Armonk
Agency: Myers Bigel Sibley & Sajovec, PA
Main IPC: H01L21/4763
IPC: H01L21/4763 ; H01L21/302

Methods of forming integrated circuit devices using modified rectangular mask patterns to increase reliability of contacts to electrically conductive lines

Abstract:

Methods of forming integrated circuit devices include forming first and second electrically conductive lines at side-by-side locations on an integrated circuit substrate. Steps are performed to selectively etch each of the first and second electrically conductive lines into a respective pair of interconnects having facing ends that are separated from each other. This selective etching step is performed using a photolithography mask having a modified-rectangular mask pattern thereon, which is configured to define a shape of the facing ends of each of the pair of interconnects.

Abstract(Chinese):

形成集成电路器件的方法包括在集成电路衬底上的并排位置形成第一和第二导电线。执行步骤以选择性地将第一和第二导电线中的每一个蚀刻成具有彼此分离的具有相对端的相应的一对互连。该选择性蚀刻步骤使用其上具有改变的矩形掩模图案的光刻掩模进行，其被配置为限定该对互连中的每一个的相对端的形状。

Public/Granted literature

US20130210223A1 METHODS OF FORMING INTEGRATED CIRCUIT DEVICES USING MODIFIED RECTANGULAR MASK PATTERNS TO INCREASE RELIABILITY OF CONTACTS TO ELECTRICALLY CONDUCTIVE LINES Public/Granted day:2013-08-15

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02	.半导体器件或其部件的制造或处理
H01L21/04	..至少具有一个跃变势垒或表面势垒的器件，例如PN结、耗尽层、载体集结层
H01L21/34	...具有H01L21/06，H01L21/16及H01L21/18各组不包含的或有或无杂质，例如掺杂材料的半导体的器件
H01L21/46	....用H01L21/36至H01L21/428各组不包含的方法或设备处理半导体材料的（在半导体材料上制作电极的入H01L21/44）
H01L21/461	.....改变半导体材料的表面物理特性或形状的，例如腐蚀、抛光、切割
H01L21/4763	......非绝缘层的沉积，例如绝缘层上的导电层、电阻层；这些层的后处理（电极的制造入H01L21/28）