Invention Grant
- Patent Title: Method for fabricating semiconductor device by damascene process
- Patent Title (中): 通过镶嵌工艺制造半导体器件的方法
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Application No.: US13441385Application Date: 2012-04-06
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Publication No.: US08796141B2Publication Date: 2014-08-05
- Inventor: Jae-Seon Yu
- Applicant: Jae-Seon Yu
- Applicant Address: KR Gyeonggi-do
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: IP & T Group LLP
- Priority: KR10-2011-0132032 20111209
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
A method for fabricating a semiconductor device includes forming a plurality of isolation patterns, isolated from each other by a plurality of trenches, over an underlying structure; forming a plurality of conductive lines filled in the trenches, forming contact holes by removing first portions of the isolation patterns, wherein the contact holes are defined by the plurality of conductive lines and second portions of the isolation patterns that remain after removing of the first portions of the isolation patterns, and forming plugs filled in the contact holes.
Public/Granted literature
- US20130149863A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE BY DAMASCENE PROCESS Public/Granted day:2013-06-13
Information query
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