Invention Grant
- Patent Title: Power semiconductor package with bottom surface protrusions
- Patent Title (中): 功率半导体封装,底面突出
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Application No.: US13532423Application Date: 2012-06-25
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Publication No.: US08796560B2Publication Date: 2014-08-05
- Inventor: Balu Balakrishnan , Brad L. Hawthorne , Stephan Bäurle
- Applicant: Balu Balakrishnan , Brad L. Hawthorne , Stephan Bäurle
- Applicant Address: US CA San Jose
- Assignee: Power Integrations, Inc.
- Current Assignee: Power Integrations, Inc.
- Current Assignee Address: US CA San Jose
- Agency: The Law Offices of Bradley J. Bereznak
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
A package includes a body that encapsulates a semiconductor die, the body having a first pair of opposing lateral sides, a second pair of opposing lateral sides, a top, and a bottom. The bottom has a primary surface and a plurality of protrusions that extend outward from the primary surface. When the package is mounted to a printed circuit board (PCB) the protrusions contact the PCB and the primary surface is disposed a first distance away from the PCB. The package further includes a plurality of leads that extend outward from the first pair of opposing lateral sides.
Public/Granted literature
- US20120273944A1 Power Semiconductor Package With Bottom Surface Protrusions Public/Granted day:2012-11-01
Information query
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