Invention Grant
- Patent Title: Buried gate transistor
- Patent Title (中): 埋栅晶体管
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Application No.: US13660956Application Date: 2012-10-25
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Publication No.: US08796762B2Publication Date: 2014-08-05
- Inventor: Richard Lindsay , Matthias Hierlemann
- Applicant: Infineon Technologies AG
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/423 ; H01L27/088

Abstract:
An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming an isolation region between a first and a second region in a substrate, forming a recess in the substrate surface, and lining the recess with a uniform oxide. Embodiments further include doping a channel region under the bottom recess surface in the first and second regions and depositing a gate electrode material in the recess. Preferred embodiments include forming source/drain regions adjacent the channel region in the first and second regions, preferably after the step of depositing the gate electrode material. Another embodiment of the invention provides a semiconductor device comprising a recess in a surface of the first and second active regions and in the isolation region, and a dielectric layer having a uniform thickness lining the recess.
Public/Granted literature
- US20130049090A1 Buried Gate Transistor Public/Granted day:2013-02-28
Information query
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