Invention Grant
- Patent Title: Positioning and socketing for semiconductor dice
- Patent Title (中): 半导体芯片的定位和插槽
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Application No.: US13114876Application Date: 2011-05-24
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Publication No.: US08797053B2Publication Date: 2014-08-05
- Inventor: Michael L. Rutigliano , Eric J. M. Moret , David Shia
- Applicant: Michael L. Rutigliano , Eric J. M. Moret , David Shia
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: G01R31/00
- IPC: G01R31/00 ; G01R1/073

Abstract:
Devices and methods useful for testing bare and packaged semiconductor dice are provided. As integrated circuit chips become smaller and increasingly complex, the interface presented by a chip for connectivity with power supplies and other components of the system into which it is integrated similarly becomes smaller and more complex. Embodiments of the invention provide micron-scale accuracy alignment capabilities for fine pitch device first level interconnect areas. Embodiments of the invention employ air-bearings to effectuate the movement and alignment of a device under test with a testing interface. Additionally, testing interfaces comprising membranes supported by thermal fluids are provided.
Public/Granted literature
- US20120299609A1 POSITIONING AND SOCKETING FOR SEMICONDUCTOR DICE Public/Granted day:2012-11-29
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