Invention Grant
- Patent Title: Semiconductor memory apparatus and bit line equalizing circuit
- Patent Title (中): 半导体存储器和位线均衡电路
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Application No.: US13341369Application Date: 2011-12-30
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Publication No.: US08797816B2Publication Date: 2014-08-05
- Inventor: Mi Hyeon Jo
- Applicant: Mi Hyeon Jo
- Applicant Address: KR Gyeonggi-do
- Assignee: SK Hynix Inc.
- Current Assignee: SK Hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: William Park & Associates Patent Ltd.
- Priority: KR10-2011-0062447 20110627
- Main IPC: G11C7/00
- IPC: G11C7/00
Abstract:
A semiconductor memory apparatus comprises bit line sense amplifier unit, and a pair of precharge elements coupled in series between a first bit line and a second bit line and having an asymmetrical contact resistance ratio.
Public/Granted literature
- US20120327731A1 SEMICONDUCTOR MEMORY APPARATUS AND BIT LINE EQUALIZING CIRCUIT Public/Granted day:2012-12-27
Information query
