Invention Grant
- Patent Title: Equivalence checking method, equivalence checking program, and equivalence checking device
- Patent Title (中): 等价检查方法,等价检查程序和等价检查装置
-
Application No.: US13769892Application Date: 2013-02-19
-
Publication No.: US08799838B2Publication Date: 2014-08-05
- Inventor: Tadaaki Tanimoto , Shintaro Imamura
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Mattingly & Malur, PC
- Priority: JP2012-038393 20120224
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Specific characteristics of a branch structure between a behavioral description and a hardware description, a structural dependence relation therebetween, and the like are extracted and used to shorten the time of processing for equivalence checking, thereby contributing to the shortening of a processing time required for equivalence checking for a high-level description and a behavioral synthesis result. Upon checking of the equivalence of a high-level description and a synthesis result obtained by performing a behavior synthesis on the high-level description according to a behavioral synthesis restriction, correspondence information between flip-flops with a feedback loop in the synthesis result and variables associated therewith with a backward data dependence relation in a high-level description is generated and used.
Public/Granted literature
- US20130227505A1 Equivalence Checking Method, Equivalence Checking Program, and Equivalence Checking Device Public/Granted day:2013-08-29
Information query