Embodiments of the disclosure relate to methods for facilitating the design of a clock grid in an integrated circuit. The method includes propagating a chip level virtual grid across a multi-level hierarchy of the integrated circuit and customizing the grid at each macro to create a customized virtual grid for each macro. The method further includes propagating the customized virtual grid for each of the plurality of macros to one of a plurality of units and customizing the chip level virtual grid at each of the plurality of units to create the customized virtual grid for each of the plurality of units. The method also includes propagating the customized virtual grid for each of the plurality of units to the chip level and combining the plurality of customized virtual grids to form the clock grid for the integrated circuit.