Invention Grant
US08799864B2 Providing SystemVerilog testing harness for a standardized testing language
有权
为标准化测试语言提供SystemVerilog测试工具
- Patent Title: Providing SystemVerilog testing harness for a standardized testing language
- Patent Title (中): 为标准化测试语言提供SystemVerilog测试工具
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Application No.: US13614877Application Date: 2012-09-13
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Publication No.: US08799864B2Publication Date: 2014-08-05
- Inventor: Junjie Chen , Xiangdong Ji
- Applicant: Junjie Chen , Xiangdong Ji
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: HIPLegal LLP
- Agent Judith A. Szepesi
- Main IPC: G06F9/44
- IPC: G06F9/44 ; G06F9/45
Abstract:
A method and apparatus to enable SystemVerilog based tools to compile, debug, and execute a standardized testing language based test bench. The testing harness comprises, in one embodiment, a translator to map TTCN-3 language to a SystemVerilog test bench, a Verilog syntax compiler and simulator database including the mapped TTCN-3 language data, and a run time system using the SystemVerilog test bench with the database including the mapped TTCN-3 language data.
Public/Granted literature
- US20130067437A1 Providing SystemVerilog Testing Harness for a Standardized Testing Language Public/Granted day:2013-03-14
Information query
