Invention Grant
- Patent Title: Semiconductor device including copper wiring and via wiring having length longer than width thereof and method of manufacturing the same
- Patent Title (中): 包括长度大于其宽度的铜布线和通孔布线的半导体器件及其制造方法
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Application No.: US14067472Application Date: 2013-10-30
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Publication No.: US08802562B2Publication Date: 2014-08-12
- Inventor: Yoshihisa Matsubara
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Kawasaki-Shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-Shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2007-038361 20070219
- Main IPC: H01L21/4763
- IPC: H01L21/4763

Abstract:
A method for manufacturing a semiconductor device includes forming a first interconnect over the semiconductor substrate; forming an interlayer dielectric film over the first interconnect; forming a hole in the interlayer dielectric film such that the hole reaches the first interconnect; forming a trench in the interlayer dielectric film; and embedded a conductive film in the hole and the trench, thereby a via is formed in the hole and a second interconnect in the trench, wherein, in a planar view, the first interconnect extends in a first direction, wherein, in a planar view, the second interconnect extends in a second direction which is perpendicular to the first direction, and wherein a maximum width of the via in the second direction is larger than a maximum width of the via in the first direction.
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