Invention Grant
- Patent Title: Semiconductor plural gate lengths
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Application No.: US13608211Application Date: 2012-09-10
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Publication No.: US08802565B2Publication Date: 2014-08-12
- Inventor: Michael J. Hartig , Sivananda K. Kanakasabapathy , Soon-Cheon Seo , Raghavasimhan Sreenivasan
- Applicant: Michael J. Hartig , Sivananda K. Kanakasabapathy , Soon-Cheon Seo , Raghavasimhan Sreenivasan
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Roberts Mlotkowski Safran & Cole, P.C.
- Agent Yuanmin Cai
- Main IPC: H01L21/302
- IPC: H01L21/302

Abstract:
Gate structures with different gate lengths and methods of manufacture are disclosed. The method includes forming a first gate structure with a first critical dimension, using a pattern of a mask. The method further includes forming a second gate structure with a second critical dimension, different than the first critical dimension of the first gate structure, using the pattern of the mask.
Public/Granted literature
- US20140070414A1 Semiconductor plural gate lengths Public/Granted day:2014-03-13
Information query
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