Pattern forming method

Invention Grant

US08802570B2 Pattern forming method 有权

Title translation: 图案形成方法

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Patent Title: Pattern forming method
Patent Title (中): 图案形成方法
Application No.: US13682619

Application Date: 2012-11-20
Publication No.: US08802570B2

Publication Date: 2014-08-12
Inventor: Kenichi Iida , Toshiki Ito
Applicant: Canon Kabushiki Kaisha
Applicant Address: JP Tokyo
Assignee: Canon Kabushiki Kaisha
Current Assignee: Canon Kabushiki Kaisha
Current Assignee Address: JP Tokyo
Agency: Canon U.S.A., Inc., IP Division
Priority: JP2011-259272 20111128
Main IPC: H01L21/311
IPC: H01L21/311

Abstract:

In a pattern forming method, a pattern having at least either a recess or a protrusion of a curable composition is formed of a curable composition by curing the curable composition into a cured film with a mold having a surface provided with at least either a recess or a protrusion, and separating the mold from the curable composition. The method includes (i) forming a gas generation region containing a gas generator agent so that the gas generation region will be disposed in contact with both the mold and the cured film between the mold and the cured film, (ii) generating a gas from the gas generation region, and (iii) separating the mold from the cured film during or after the step of (ii).

Abstract(Chinese):

在图案形成方法中，具有固化性组合物的凹部或突起中的至少任一种的图案由固化性组合物形成，该固化性组合物通过使具有表面的模具固化成固化膜而形成固化膜，所述模具具有至少一个凹部突起，并将模具与可固化组合物分离。该方法包括：（i）形成含有气体发生剂的气体产生区域，使得气体产生区域将与模具和固化膜之间的模具和固化膜两者相接触，（ii）产生气体从气体产生区域，和（iii）在（ii）的步骤期间或之后将模具与固化膜分离。

Public/Granted literature

US20130137252A1 PATTERN FORMING METHOD Public/Granted day:2013-05-30

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02	.半导体器件或其部件的制造或处理
H01L21/04	..至少具有一个跃变势垒或表面势垒的器件，例如PN结、耗尽层、载体集结层
H01L21/18	...器件有由周期表Ⅳ族元素或含有/不含有杂质的AⅢBⅤ族化合物构成的半导体，如掺杂材料
H01L21/30	....用H01L21/20至H01L21/26各组不包含的方法或设备处理半导体材料的（在半导体材料上制作电极的入H01L21/28）
H01L21/31	.....在半导体材料上形成绝缘层的，例如用于掩膜的或应用光刻技术的（密封层入H01L21/56）；以及这些层的后处理；这些层的材料的选择
H01L21/3105	......后处理
H01L21/311	.......绝缘层的刻蚀