Invention Grant
- Patent Title: Semiconductor package and manufacturing method thereof
- Patent Title (中): 半导体封装及其制造方法
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Application No.: US13169335Application Date: 2011-06-27
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Publication No.: US08803304B2Publication Date: 2014-08-12
- Inventor: Yohei Igarashi , Yasushi Araki
- Applicant: Yohei Igarashi , Yasushi Araki
- Applicant Address: JP Nagano-shi, Nagano
- Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee Address: JP Nagano-shi, Nagano
- Agency: Drinker Biddle & Reath LLP
- Priority: JP2010-147196 20100629
- Main IPC: H01L23/34
- IPC: H01L23/34

Abstract:
There is provided a semiconductor package that includes: a wiring board; a first semiconductor chip mounted on the wiring board; a second semiconductor chip mounted on the first semiconductor chip, wherein a size of second semiconductor chip is larger than that of the first semiconductor chip when viewed from a thickness direction of the semiconductor package; an insulating resin provided between the wiring board and the second semiconductor chip and between the wiring board and the first semiconductor chip so as to cover the first semiconductor chip; a base disposed on the wiring board to face a surface of the second semiconductor chip, wherein the insulating resin is provided between the base and the second semiconductor chip so as to cover the base.
Public/Granted literature
- US20110316172A1 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF Public/Granted day:2011-12-29
Information query
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