Invention Grant
- Patent Title: Semiconductor chips including passivation layer trench structure
- Patent Title (中): 半导体芯片包括钝化层沟槽结构
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Application No.: US13852296Application Date: 2013-03-28
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Publication No.: US08803318B2Publication Date: 2014-08-12
- Inventor: Deepak Kulkarni , Michael W. Lane , Satyanayana V. Nitta , Shom Ponoth
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Matthew Zehrer
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer.
Public/Granted literature
- US20130207263A1 SEMICONDUCTOR CHIPS INCLUDING PASSIVATION LAYER TRENCH STRUCTURE Public/Granted day:2013-08-15
Information query
IPC分类: