Invention Grant
- Patent Title: Semiconductor package and stacked semiconductor package
- Patent Title (中): 半导体封装和堆叠半导体封装
-
Application No.: US13892538Application Date: 2013-05-13
-
Publication No.: US08803329B2Publication Date: 2014-08-12
- Inventor: Takashi Aoki
- Applicant: Canon Kabushiki Kaisha
- Applicant Address: JP Tokyo
- Assignee: Canon Kabushiki Kaisha
- Current Assignee: Canon Kabushiki Kaisha
- Current Assignee Address: JP Tokyo
- Agency: Fitzpatrick, Cella, Harper & Scinto
- Priority: JP2012-122975 20120530
- Main IPC: H01L23/495
- IPC: H01L23/495
Abstract:
A semiconductor package includes a printed wiring board and a semiconductor chip that has a first signal terminal and a second signal terminal and is mounted on the printed wiring board. The printed wiring board has a first land and a second land for solder joining, which are formed on a surface layer thereof. Further, the printed wiring board has a first wiring for electrically connecting the first signal terminal of the semiconductor chip and the first land, and a second wiring for electrically connecting the second signal terminal of the semiconductor chip and the second land. The second wiring is formed so that the wiring length thereof is larger than that of the first wiring. The second land is formed so that the surface area thereof is larger than that of the first land. This reduces difference in transmission line characteristics due to the difference in wiring length.
Public/Granted literature
- US20130320568A1 SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE Public/Granted day:2013-12-05
Information query
IPC分类:
