A semiconductor package including a substrate, a chip stack portion disposed on the substrate and including a plurality of first semiconductor chips, at least one second semiconductor chip disposed on the chip stack portion, and a signal transmitting medium to electrically connect the at least one second semiconductor chip and the substrate to each other, such that the chip stack portion is a parallelepiped structure including a first chip that is a semiconductor chip of the plurality of first semiconductor chips and includes a through silicon via (TSV), a second chip that is another semiconductor chip of the plurality of first semiconductor chips and electrically connected to the first chip through the TSV, and an internal sealing member to fill a space between the first chip and the second chip.