An electronic storage device includes a bit cell circuit, feedback circuit, and read accelerator circuit. The bit cell circuit is adapted for connection with true and complementary bit lines. The feedback circuit includes a first transistor which is coupled to a first voltage potential and responsive to the complementary bit line. The read accelerator circuit includes second, third, and fourth transistors coupled between the feedback circuit and a second voltage potential. The second transistor is responsive to a read line, the third transistor is responsive to the true bit line, and the fourth transistor is responsive to the complementary bit line. The read accelerator circuit is configured to provide a discharge path for at least one of the true bit line and the complementary bit line during a read access of the bit cell. Embodiments of a corresponding electronic read access accelerator device and method are also provided.