Invention Grant
- Patent Title: Multi-serial interface stacked-die memory architecture
- Patent Title (中): 多串行接口堆叠存储器架构
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Application No.: US13179156Application Date: 2011-07-08
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Publication No.: US08806131B2Publication Date: 2014-08-12
- Inventor: Joe M. Jeddeloh , Paul A. LaBerge
- Applicant: Joe M. Jeddeloh , Paul A. LaBerge
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: H04L12/28
- IPC: H04L12/28 ; H04L12/56 ; G06F13/00 ; G06F13/28

Abstract:
Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding plurality of serialized communication link interfaces (SCLIs) between one or more originating devices or destination devices such as a processor and a switch. At the switch, one or more commands, addresses, or data corresponding to each stream can be transferred to a corresponding destination memory vault controller (MVC) associated with a corresponding memory vault. The destination MVC can perform write operations, read operations, and/or memory vault housekeeping operations independently from concurrent operations associated with other MVCs coupled to a corresponding plurality of memory vaults.
Public/Granted literature
- US20110264858A1 MULTI-SERIAL INTERFACE STACKED-DIE MEMORY ARCHITECTURE Public/Granted day:2011-10-27
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