Invention Grant
- Patent Title: Load store unit with load miss result buffer
- Patent Title (中): 加载存储单元与加载未结果缓冲区
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Application No.: US13250481Application Date: 2011-09-30
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Publication No.: US08806135B1Publication Date: 2014-08-12
- Inventor: Matthew W. Ashcraft , John Gregory Favor , David A. Kruckemyer
- Applicant: Matthew W. Ashcraft , John Gregory Favor , David A. Kruckemyer
- Applicant Address: US CA Sunnyvale
- Assignee: Applied Micro Circuits Corporation
- Current Assignee: Applied Micro Circuits Corporation
- Current Assignee Address: US CA Sunnyvale
- Agency: Amin, Turocy & Watson, LLP
- Main IPC: G06F12/08
- IPC: G06F12/08

Abstract:
A load/store unit with an outstanding load miss buffer and a load miss result buffer is configured to read data from a memory system having a level one cache. Missed load instructions are stored in the outstanding load miss buffer. The load/store unit retrieves data for multiple dependent missed load instructions using a single cache access and stores the data in the load miss result buffer. When missed load instructions are reissued from the outstanding load miss buffer, data for the missed load instructions are read from the load miss result buffer rather than the level one cache. Because the data is stored in the load miss result buffer, other instructions that may change the data in level one cache do not cause data hazards with the missed load instructions.
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