Invention Grant
- Patent Title: Sub-resolution assist feature arranging method and computer program product and manufacturing method of semiconductor device
- Patent Title (中): 分解辅助功能布置方法和计算机程序产品及半导体器件的制造方法
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Application No.: US13051961Application Date: 2011-03-18
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Publication No.: US08809072B2Publication Date: 2014-08-19
- Inventor: Chikaaki Kodama , Toshiya Kotani , Shigeki Nojima , Shoji Mimotogi
- Applicant: Chikaaki Kodama , Toshiya Kotani , Shigeki Nojima , Shoji Mimotogi
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2010-123100 20100528
- Main IPC: H01L21/66
- IPC: H01L21/66 ; G01R31/26
Abstract:
According to a sub-resolution assist feature arranging method in embodiments, it is selected which of a rule base and a model base is set for which pattern region on pattern data corresponding to a main pattern as a type of the method of arranging the sub-resolution assist feature for improving resolution of the main pattern formed on a substrate. Then, the sub-resolution assist feature by the rule base is arranged in a pattern region set as the rule base and the sub-resolution assist feature by the model base is arranged in a pattern region set as the model base.
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Information query
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