Invention Grant
US08809106B2 Method for semiconductor sensor structures with reduced dislocation defect densities
有权
具有减少位错缺陷密度的半导体传感器结构的方法
- Patent Title: Method for semiconductor sensor structures with reduced dislocation defect densities
- Patent Title (中): 具有减少位错缺陷密度的半导体传感器结构的方法
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Application No.: US13594519Application Date: 2012-08-24
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Publication No.: US08809106B2Publication Date: 2014-08-19
- Inventor: Zhiyuan Cheng , James Fiorenza , Calvin Sheen , Anthony J. Lochtefeld
- Applicant: Zhiyuan Cheng , James Fiorenza , Calvin Sheen , Anthony J. Lochtefeld
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater and Matsil, L.L.P.
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/02 ; H01L31/105

Abstract:
Non-silicon based semiconductor devices are integrated into silicon fabrication processes by using aspect-ratio-trapping materials. Non-silicon light-sensing devices in a least a portion of a crystalline material can output electrons generated by light absorption therein. Exemplary light-sensing devices can have relatively large micron dimensions. As an exemplary application, complementary-metal-oxide-semiconductor photodetectors are formed on a silicon substrate by incorporating an aspect-ratio-trapping technique.
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