Invention Grant
- Patent Title: High performance CMOS transistors using PMD liner stress
- Patent Title (中): 使用PMD衬垫应力的高性能CMOS晶体管
-
Application No.: US11670192Application Date: 2007-02-01
-
Publication No.: US08809141B2Publication Date: 2014-08-19
- Inventor: Haowen Bu , Rajesh Khamankar , Douglas T. Grider
- Applicant: Haowen Bu , Rajesh Khamankar , Douglas T. Grider
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Frederick J. Telecky, Jr.
- Main IPC: H01L29/739
- IPC: H01L29/739
Abstract:
A silicon nitrate layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting the first tensile stress into a second tensile stress that is larger than the first tensile stress. Following the thermal anneal, the hydrogen concentration in the silicon nitride layer (110) is greater than 12 atomic percent.
Public/Granted literature
- US20070128806A1 High performance CMOS transistors using PMD liner stress Public/Granted day:2007-06-07
Information query
IPC分类:
