Invention Grant
US08809179B2 Method for reducing topography of non-volatile memory and resulting memory cells
有权
减少非易失性存储器和结果存储单元的形貌的方法
- Patent Title: Method for reducing topography of non-volatile memory and resulting memory cells
- Patent Title (中): 减少非易失性存储器和结果存储单元的形貌的方法
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Application No.: US11716164Application Date: 2007-03-09
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Publication No.: US08809179B2Publication Date: 2014-08-19
- Inventor: Shih Wei Wang , Derek Lin , Chen-Ming Huang , Chang-Jen Hsieh , Chi-Hsin Lo , Chung-Yi Yu , Feng-Jia Shiu , Yeur-Luen Tu , Yi-Shin Chu , Jen-Sheng Yang
- Applicant: Shih Wei Wang , Derek Lin , Chen-Ming Huang , Chang-Jen Hsieh , Chi-Hsin Lo , Chung-Yi Yu , Feng-Jia Shiu , Yeur-Luen Tu , Yi-Shin Chu , Jen-Sheng Yang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater and Matsil, L.L.P.
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L27/115 ; H01L27/105
Abstract:
A method for forming a semiconductor structure includes providing a substrate; forming a gate stack of a flash memory cell, wherein a top portion of the gate stack comprises a capping layer; forming a gate having at least a portion over the capping layer; and reducing a thickness of the portion of the gate over the capping layer. The topography height difference between the flash memory cell and MOS devices on the same chip is reduced.
Public/Granted literature
- US20070241386A1 Method for reducing topography of non-volatile memory and resulting memory cells Public/Granted day:2007-10-18
Information query
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