Invention Grant
- Patent Title: Patterned dummy wafers loading in batch type CVD
- Patent Title (中): 图案化的假晶片以分批式CVD方式装载
-
Application No.: US13022517Application Date: 2011-02-07
-
Publication No.: US08809206B2Publication Date: 2014-08-19
- Inventor: Rinji Sugino , Bradley Marc Davis , Lei Xue , Kenichi Ohtsuka
- Applicant: Rinji Sugino , Bradley Marc Davis , Lei Xue , Kenichi Ohtsuka
- Applicant Address: US CA Sunnyvale
- Assignee: Spansion LLC
- Current Assignee: Spansion LLC
- Current Assignee Address: US CA Sunnyvale
- Agency: Sterne, Kessler, Goldstein & Fox PLLC
- Main IPC: H01L21/31
- IPC: H01L21/31

Abstract:
A method for semiconductor device fabrication is provided. The present invention is directed towards using at least one patterned dummy wafer along with one or more product wafers in a film deposition system to create a sidewall layer thickness variation that is substantially uniform across all product wafers. The at least one patterned dummy wafer may have a high density patterned substrate surface with a topography that is different from or substantially similar to a topography of the one or more product wafers. Furthermore, in a batch type Chemical Vapor Deposition (CVD) system, the at least one patterned dummy wafer may be placed near a gas inlet of the CVD system. At least one patterned dummy wafer may be placed near an exhaust of the CVD system. Additionally, the patterned dummy wafers may be reusable in subsequent film deposition processes.
Public/Granted literature
- US20120202355A1 PATTERNED DUMMY WAFERS LOADING IN BATCH TYPE CVD Public/Granted day:2012-08-09
Information query
IPC分类: