Invention Grant
- Patent Title: Semiconductor device having a pad and plurality of interconnects
- Patent Title (中): 具有焊盘和多个互连的半导体器件
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Application No.: US13323454Application Date: 2011-12-12
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Publication No.: US08810039B2Publication Date: 2014-08-19
- Inventor: Koji Takemura , Hiroshige Hirano , Masao Takahashi , Hikari Sano , Yutaka Itoh , Koji Koike
- Applicant: Koji Takemura , Hiroshige Hirano , Masao Takahashi , Hikari Sano , Yutaka Itoh , Koji Koike
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2005-254852 20050902
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/00 ; H01L21/66
Abstract:
A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.
Public/Granted literature
- US20120080780A1 SEM ICONDUCTOR DEVICE HAVING PADS AND WHICH MINIMIZES DEFECTS DUE TO BONDING AND PROBING PROCESSES Public/Granted day:2012-04-05
Information query
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