Invention Grant
- Patent Title: CMOS transistor linearization method
- Patent Title (中): CMOS晶体管线性化方法
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Application No.: US13477838Application Date: 2012-05-22
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Publication No.: US08810283B2Publication Date: 2014-08-19
- Inventor: Joseph M. Hensley , Franklin M. Murden
- Applicant: Joseph M. Hensley , Franklin M. Murden
- Applicant Address: US MA Norwood
- Assignee: Analog Devices, Inc.
- Current Assignee: Analog Devices, Inc.
- Current Assignee Address: US MA Norwood
- Agency: Kenyon & Kenyon LLP
- Main IPC: G11C27/02
- IPC: G11C27/02

Abstract:
A circuit for sampling an analog input signal may include a transistor disposed on a substrate and a sampling capacitor coupled to one of the source and the drain of the transistor. The transistor may be disposed on a substrate that is coupled to ground. A source and a drain of the transistor may be disposed in a back gate of the transistor. The analog input may be supplied to one of the source and the drain of the transistor, and the back gate may receive a back gate voltage having a value that is lower than ground.
Public/Granted literature
- US20130314128A1 CMOS TRANSISTOR LINEARIZATION METHOD Public/Granted day:2013-11-28
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