An output buffer is disclosed. The output buffer includes an input-stage circuit, an output-stage circuit and a compensation circuit. The compensation circuit includes a capacitor, a first switch, a second switch, a third switch, and a fourth switch. The input-stage circuit receives a differential input signal and outputting a response signal. The output-stage circuit receives the response signal and outputting an output signal. The first switch controls a connection between the input-stage circuit and a first terminal of the capacitor. The second switch controls the connection between an output terminal of the compensation circuit and a second terminal of the capacitor. The third switch controls the connection between the input-stage circuit and the second-terminal of the capacitor. The forth switch controls the connection between the output terminal of the compensation circuit and the first terminal of the capacitor.