Invention Grant
- Patent Title: Laminated inductor element and manufacturing method thereof
- Patent Title (中): 层叠电感器元件及其制造方法
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Application No.: US13955505Application Date: 2013-07-31
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Publication No.: US08810352B2Publication Date: 2014-08-19
- Inventor: Tomoya Yokoyama , Takako Sato , Akihiro Ieda , Shigetoshi Hayashi , Hirokazu Yazaki
- Applicant: Murata Manufacturing Co., Ltd.
- Applicant Address: JP Kyoto
- Assignee: Murata Manufacturing Co., Ltd.
- Current Assignee: Murata Manufacturing Co., Ltd.
- Current Assignee Address: JP Kyoto
- Agency: Keating & Bennett, LLP
- Priority: JP2011-086899 20110411
- Main IPC: H01F5/00
- IPC: H01F5/00 ; H01F27/29 ; H01L23/12 ; H01F41/04 ; H01F17/00 ; H01F3/14

Abstract:
In a laminated inductor element, outer electrodes and terminal electrodes are electrically connected by via holes, internal wiring lines, and end surface electrodes. The via holes on an upper surface side are provided immediately under the outer electrodes and in a non-magnetic ferrite layer. The via holes on a lower surface side are provided immediately above the terminal electrodes and in a non-magnetic ferrite layer. Since outermost layers are defined by the non-magnetic ferrite layers, a parasitic inductance is not increased, even if the outermost layers are provided with the via holes. In this case, the internal wiring lines are not routed on a surface of the element. Therefore, there is no complication of a wiring pattern, and it is possible to prevent an increase in a mounting area of the element.
Public/Granted literature
- US20130314190A1 LAMINATED INDUCTOR ELEMENT AND MANUFACTURING METHOD THEREOF Public/Granted day:2013-11-28
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