Invention Grant
US08811059B2 Resistive memory apparatus, layout structure, and sensing circuit thereof
有权
电阻式存储装置，布局结构及其检测电路
- Patent Title: Resistive memory apparatus, layout structure, and sensing circuit thereof
- Patent Title (中): 电阻式存储装置，布局结构及其检测电路
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Application No.: US13339159Application Date: 2011-12-28
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Publication No.: US08811059B2Publication Date: 2014-08-19
- Inventor: Kwang Myoung Rho
- Applicant: Kwang Myoung Rho
- Applicant Address: KR Gyeonggi-do
- Assignee: SK Hynix Inc.
- Current Assignee: SK Hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: William Park & Associates Patent Ltd.
- Priority: KR10-2011-0104512 20111013
- Main IPC: G11C11/00
- IPC: G11C11/00
Abstract:
Provided is a resistive memory apparatus including a plurality of memory areas each including a main memory cell array coupled to a plurality of word lines and a reference cell array coupled to a plurality of reference word lines. Each of the memory areas shares a bit line driver/sinker with an adjacent memory area.
Public/Granted literature
- US20130094277A1 RESISTIVE MEMORY APPARATUS, LAYOUT STRUCTURE, AND SENSING CIRCUIT THEREOF Public/Granted day:2013-04-18
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