Invention Grant
US08811528B2 Methods and apparatus for transmitting signals with selective delay for compensation of intersymbol interference and simultaneous switching outputs 有权
用于传输信号的选择性延迟的方法和装置,用于对符号间干扰和同时开关输出进行补偿

  • Patent Title: Methods and apparatus for transmitting signals with selective delay for compensation of intersymbol interference and simultaneous switching outputs
  • Patent Title (中): 用于传输信号的选择性延迟的方法和装置,用于对符号间干扰和同时开关输出进行补偿
  • Application No.: US12954028
    Application Date: 2010-11-24
  • Publication No.: US08811528B2
    Publication Date: 2014-08-19
  • Inventor: Thomas HughesVictor K. Suen
  • Applicant: Thomas HughesVictor K. Suen
  • Applicant Address: US CA San Jose
  • Assignee: LSI Corporation
  • Current Assignee: LSI Corporation
  • Current Assignee Address: US CA San Jose
  • Agency: Ryan, Mason & Lewis, LLP
  • Main IPC: H04L25/49
  • IPC: H04L25/49
Methods and apparatus for transmitting signals with selective delay for compensation of intersymbol interference and simultaneous switching outputs
Abstract:
Transmitter-based techniques are provided for compensation of intersymbol interference and/or simultaneous switching outputs, using selective pulse width modulation. One or more signals are transmitted by detecting whether one or more of said signals satisfy one or more predefined signal corruption conditions, wherein said predefined signal corruption conditions indicate that one or more of said signals are anticipated to exhibit one or more of intersymbol interference and simultaneous switching outputs; and selecting a delay for one or more of the signals based on the one or more predefined signal corruptions conditions. The predefined signal corruption conditions comprise, for example, (i) digital data encoded in the one or more signals maintaining a same binary value for two or more consecutive clock cycles (to indicate intersymbol interference); and (ii) a predefined minimum number of aggressor data edges in digital data encoded in the one or more signals, and a corresponding predefined number of victim data edges in the digital data encoded in the one or more signals, wherein the victim edges are moving in an opposite direction to the aggressor data edges (to indicate simultaneous switching outputs).
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