Invention Grant
US08812414B2 Low-power event-driven neural computing architecture in neural networks
有权
神经网络中的低功率事件驱动神经计算架构
- Patent Title: Low-power event-driven neural computing architecture in neural networks
- Patent Title (中): 神经网络中的低功率事件驱动神经计算架构
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Application No.: US13149754Application Date: 2011-05-31
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Publication No.: US08812414B2Publication Date: 2014-08-19
- Inventor: John V. Arthur , Paul A. Merolla , Dharmendra S. Modha
- Applicant: John V. Arthur , Paul A. Merolla , Dharmendra S. Modha
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Sherman & Zarrabian LLP
- Agent Kenneth L. Sherman, Esq.; Michael Zarrabian, Esq.
- Main IPC: G06E1/00
- IPC: G06E1/00 ; G06E3/00 ; G06F15/18 ; G06G7/00 ; G06N3/02

Abstract:
A neural network includes an electronic synapse array of multiple digital synapses interconnecting a plurality of digital electronic neurons. Each synapse interconnects an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron. Each neuron integrates input spikes and generates a spike event in response to the integrated input spikes exceeding a threshold. A decoder receives spike events sequentially and transmits the spike events to selected axons in the synapse array. An encoder transmits spike events corresponding to spiking neurons. A controller coordinates events from the synapse array to the neurons, and signals when neurons may compute their spike events within each time step, ensuring one-to-one correspondence with an equivalent software model. The synapse array includes an interconnecting crossbar that sequentially receives spike events from axons, wherein one axon at a time drives the crossbar, and the crossbar transmits synaptic events in parallel to multiple neurons.
Public/Granted literature
- US20140114893A1 LOW-POWER EVENT-DRIVEN NEURAL COMPUTING ARCHITECTURE IN NEURAL NETWORKS Public/Granted day:2014-04-24
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